QUOTE(bjouan @ Sep 27 2013, 03:58 AM)

Just to give more details, I have already tried un-bridge U6T1 and make some measures from capacitors from CPU and GPU. The resistance from decoupling capacitors from CPU shows 8.8 Ohms and from decoupling capacitors from GPU shows 2.7 Ohms.
Reading the Microsoft debug manual, what I found online, those measures are corrects. Does someone have any difference?
Regards,
bjouan
Guys please some help here!
After lots of hours debugging the hardware I have found some odd stuff. The correct booting flow chart is:
1. Power OnDetected? Wait until ok
2. SMC Sends PSU_V12P0_EN
3. SMC Receives ANA_V12P0_PWRGD
4. SMC Enables VREG_GPU_EN_N
5. Received VREG_GPU_PWRGD? Wait until ok
6. SMC Enables 5V, Vmem and 3V3 Vregs (VREG_3P3_EN Jasper)
7. SMC Enables ANA_CLK_OE
8. SMC Enables VREG_CPU_EN
9. Received VREG_CPU_PWRGD? Wait until ok
However I have noticed that until step 6 everything goes ok, but at step 6 the SMC sends VREG_V5P0_EN and VREG_V1P8_EN at the same time enabling the V_5P0 (5.07 V) and V_MEM (1.89 V) respectively. Then the SMC receives the signal from IC U4V1 VREG_V5P0_VMEM_PWRGD. So far so good, but the odd stuff is the missing signal VREG_3P3_EN which supposedly would enable the IC U1F1 and the V_3P3.
I was wonder if I wire up the VREG_3P3_EN together with VREG_V5P0_EN or VREG_V1P8_EN!
Please guys I really appreciate any help!!!