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[Ranger72]

This would have saved me about 10 hours of try and error on my first Slim. I would get the wire length just right and spooled around under the board just right to get it to boot under 5 seconds only to have it to all to shit when I put it back into the cage and have to mess with the wire length again.


There are some Slims out there that are much more picky than others. For those this device would come in handy.

[shtewps]

You are sad, and 100% oblivious.

Were not talking about a test lab here you dumb sh*t (since you want to start name calling). Were talking about running a business and offering quality product to a consumer market.

You want to talk about testing, eh? Really? I bet your definition of 'testing' fits nicely with that of TX. Let's sell these "bitches" a product, let them do the leg work, and capitalize off their findings. Because it only took them an extra 3 months of "testing" to come out with a kit that wasn't complete. And this is not even mentioning BB jaspers that require a cap.

Oh f*ck yeah bud, so much "testing" going on here.

Please, do everyone a favour and don't associate yourself with the business world. Pathetic child.

QUOTE(xiaNaix @ Dec 5 2011, 03:33 PM)

You dont think this stuff is tested while its being made ? So naive.....

[Blackaddr]

QUOTE(pif001 @ Dec 5 2011, 08:29 PM)

Please share a tutorial about optimizing our own JED files... and ignore that troll please!

Before you get into exotic ideas like long loops of cables, a ton of different cap values, give yourself the best chance at success first, then move on to more complex ideas.  Put the CPLD board as close to the CPU_RST as you can reasonably get it, atleast for initial testing.  You can always move it to a more convenient location later once you've established boot times with a very short wire.  Then you know what the real impact is.


As for changing the source code, Gligli posted all his source code to build your own JED on github.  Try to compile his source code as-is using the free ISE Webpack tools (you can probably find general tutorials and guides on using ISE on the web, and ask around for help).  Make sure you can compile the unaltered code, program the CPLD and it still works.  This proves you're compiling correctly.  Just learning this part will be the hardest, but it's worthwhile.

Then, find the following line in slim.vhd:

constant WIDTH_RESET_START  : integer := 17357;

That's the one you will change.

Try changing the value from 17357 to 17358.  See if it still works, does it work better?  Try 17356, same thing, does it still work, is it any more reliable?

It probably sounds like a pain to have to change the code, recompile, reprogram and test.  But If 17357 isn't already optimal for your console, then the best value will be very close, like, +/1 or +/- 2 at the most, so you really don't need to try many different values.

[shtewps]

Now if that wasn't constructive, I don't know what is. Thanks for the insight Blackaddr.

QUOTE(Blackaddr @ Dec 5 2011, 11:03 PM)

Before you get into exotic ideas like long loops of cables, a ton of different cap values, give yourself the best chance at success first, then move on to more complex ideas.  Put the CPLD board as close to the CPU_RST as you can reasonably get it, atleast for initial testing.  You can always move it to a more convenient location later once you've established boot times with a very short wire.  Then you know what the real impact is.
As for changing the source code, Gligli posted all his source code to build your own JED on github.  Try to compile his source code as-is using the free ISE Webpack tools (you can probably find general tutorials and guides on using ISE on the web, and ask around for help).  Make sure you can compile the unaltered code, program the CPLD and it still works.  This proves you're compiling correctly.  Just learning this part will be the hardest, but it's worthwhile.

Then, find the following line in slim.vhd:

constant WIDTH_RESET_START  : integer := 17357;

That's the one you will change.

Try changing the value from 17357 to 17358.  See if it still works, does it work better?  Try 17356, same thing, does it still work, is it any more reliable?

It probably sounds like a pain to have to change the code, recompile, reprogram and test.  But If 17357 isn't already optimal for your console, then the best value will be very close, like, +/1 or +/- 2 at the most, so you really don't need to try many different values.

[ruciz]

QUOTE(Ranger72 @ Dec 6 2011, 01:01 AM)

This would have saved me about 10 hours of try and error on my first Slim. I would get the wire length just right and spooled around under the board just right to get it to boot under 5 seconds only to have it to all to shit when I put it back into the cage and have to mess with the wire length again.
There are some Slims out there that are much more picky than others. For those this device would come in handy.

Serious? 10 hours to tape wire?

Totally not worth it. save 10 sec on a boot, be 10 years before I would notice that amount of time saving.

QUOTE(Blackaddr @ Dec 6 2011, 04:03 AM)

Before you get into exotic ideas like long loops of cables, a ton of different cap values, give yourself the best chance at success first, then move on to more complex ideas.  Put the CPLD board as close to the CPU_RST as you can reasonably get it, atleast for initial testing.  You can always move it to a more convenient location later once you've established boot times with a very short wire.  Then you know what the real impact is.
As for changing the source code, Gligli posted all his source code to build your own JED on github.  Try to compile his source code as-is using the free ISE Webpack tools (you can probably find general tutorials and guides on using ISE on the web, and ask around for help).  Make sure you can compile the unaltered code, program the CPLD and it still works.  This proves you're compiling correctly.  Just learning this part will be the hardest, but it's worthwhile.

Then, find the following line in slim.vhd:

constant WIDTH_RESET_START  : integer := 17357;

That's the one you will change.

Try changing the value from 17357 to 17358.  See if it still works, does it work better?  Try 17356, same thing, does it still work, is it any more reliable?

It probably sounds like a pain to have to change the code, recompile, reprogram and test.  But If 17357 isn't already optimal for your console, then the best value will be very close, like, +/1 or +/- 2 at the most, so you really don't need to try many different values.

kudos for this tidbit of information. Its greatly appreciated.

[pif001]

Thnx Blackaddr. You explained it well....

[Tag234]

'xiaNaix' - you sir, are either seriously misinformed or are just working for TX.

Thanks for that info Blackaddr

[Exobex]

QUOTE(Blackaddr @ Dec 6 2011, 03:03 AM)

Before you get into exotic ideas like long loops of cables, a ton of different cap values, give yourself the best chance at success first, then move on to more complex ideas.  Put the CPLD board as close to the CPU_RST as you can reasonably get it, atleast for initial testing.  You can always move it to a more convenient location later once you've established boot times with a very short wire.  Then you know what the real impact is.
As for changing the source code, Gligli posted all his source code to build your own JED on github.  Try to compile his source code as-is using the free ISE Webpack tools (you can probably find general tutorials and guides on using ISE on the web, and ask around for help).  Make sure you can compile the unaltered code, program the CPLD and it still works.  This proves you're compiling correctly.  Just learning this part will be the hardest, but it's worthwhile.

Then, find the following line in slim.vhd:

constant WIDTH_RESET_START  : integer := 17357;

That's the one you will change.

Try changing the value from 17357 to 17358.  See if it still works, does it work better?  Try 17356, same thing, does it still work, is it any more reliable?

It probably sounds like a pain to have to change the code, recompile, reprogram and test.  But If 17357 isn't already optimal for your console, then the best value will be very close, like, +/1 or +/- 2 at the most, so you really don't need to try many different values.

I've not meddled with CPLD programming at all, but does this mean that a DIY-even-for-newbies version would be possible? I'm thinking a 4-gang DIP switch on the PCB, which would, for example, allow a range from 17350 to 17365 to be selected, or 17354 to 17341 with a spare switch for something else? Obviously this depends on how the code uses the WIDTH_RESET_START constant gets used wirhin the code, and if there are spare I/O pins available to read the switches.

[cornnatron]

Tnx for the explaination of the timming blackaddr will have a look at ISE tonight .

[rastiemon]

I don't know what to think of this wire and coil length stuff.   I have glitched about 30 slims to this point and never really had a issue with extreme boot times nothing over 45 seconds or so.   Then I worked on a slim this week that just didnt want to glitch constantly at all.   Tried every combo of coil shape, wire length etc.  It would boot 1 min, 6, never, 4min, 6min,  and once every 20 boots or so it would boot under 20 seconds.  I even tried a different coolrunner.  

So I can understand peoples frustration if their only box has issues like that one.  But so far the coolrunner has given me great boot times on most slims so far.  Im hoping the last batch I ordered wasn't an issue also.   I am gonna try to glitch another box with the same 2 chips I used on the last and see how that goes.

[rastiemon]

Im gonna have a go messing around with the programming also.   I would rather do that then sit and play with wire lengths all night.

[Julets]

QUOTE(Blackaddr @ Dec 5 2011, 04:29 PM)

This is getting out of hand with all these silly wire lengths and loops.

If you install your CPLD board right next to the CPU_RST point, and keep the wire under 1" there shouldn't be any interference on that signal.  Why does everyone insist on putting it on top of the AVIP? Sure it's easy, but you're giving yourself bigger headaches.

If you try different timing values in the CPLD you can also optimize the timing for your particular console.  Why spends days playing with wire lengths, spend an afternoon to learn to compile you own JED.

50 cm wires with loops?  Come on, KISS.

I believe at this point, you mean Ki$$, or KiMM (Keep it making money). I'm just saying...

[BerT69]

Is the topic now dead??..when and where is release for the item. I have found nothing on the hardware sites.

[jayboy86]

QUOTE(BerT69 @ Dec 10 2011, 05:30 PM)

Is the topic now dead??..when and where is release for the item. I have found nothing on the hardware sites.

I second that question

[kipper2k]

 I've seen a lot of pictures that peopple show with their wires all over the place, heres a nice simple solution, a piece of cardboard, some scotch tape and wire that is zigzagged to make up the desired length, you could even shield it if you want by putting some tin foil on the top side of the cardboard and then lay the wires.

Heres a pic of a cheap, tidy and simple solution that will save you buying the board